![]() ![]() The cookie is used to store the user consent for the cookies in the category "Analytics". ![]() This cookie is set by GDPR Cookie Consent plugin. These cookies ensure basic functionalities and security features of the website, anonymously. Necessary cookies are absolutely essential for the website to function properly. What do you think? Do you agree with the above or would you augment / modify my description in any way? Now that FPGA designs have become so pervasive, I think it’s much simpler to think in terms of the total number of LCs/LEs in a device, and to then think of the various large functional blocks in the design in terms of the number of LCs/LEs they consume (remembering that a LC/LE in one FPGA may be radically different to a LC/LE in another FPGA). So… the end result (as far as I’m concerned) is that it’s really meaningless to think in terms of system gates and/or equivalent gates in the context of FPGAs. Each of these LUTs may have anywhere from 3 to 8 inputs depending on the FPGA architecture. Each of these LCs/LEs will contain some number of LUTs. Each FPGA will boast some number of LCs/LEs. With regard to the programmable logic fabric itself – I don’t have a clue. In the case of blocks of memory, it’s best to just think about these in terms of kilo/mega bits and/or bytes – as far as I’m concerned it really makes no sense to consider these blocks in terms of equivalent gates (actually there is an exception to this, but let's not go there…). In the case of hard macros like the Cortex-M3 microcontroller in Actel’s SmartFusion devices, for example, it’s common to say things like “This core is the equivalent to 10 million gates”. The end result was that a system gate from one FPGA vendor might represent a radically different number of equivalent gates as compared to a system gate from another vendor.Īnd then things started to become complicated (grin), because today’s FPGAs don’t just contain programmable logic – they also contain hard macros and blocks of memory. In both cases, this could result in a sub-optimal mapping into the FPGA.Īnd things became even more complicated if an FPGA vendor went through an intermediate step of equating system gates to LCs/LEs – not the least that different FPGA architectures might boast LCs/LEs with different numbers of LUTs, and the LUTs themselves could have different numbers of inputs. This was because some ASIC designs might be predominately combinatorial, while others might make excessively heavy use of registers. Now, the FPGA vendor could proudly say “our FPGA can implement XXX system gates,” then somewhere in the fine-print they would say “One system gate is equivalent to YYY logic gates.”īut things are never simple, because even assuming that one was talking about an FPGA containing only rudimentary programmable fabric, it would be difficult to state with certainly whether or not a particular ASIC design containing XXX equivalent gates could fit into an FPGA containing YYY system gates. The idea was that each system gate was the equivalent to some number of regular logic gates. In order to address this issue, in the early 1990s, FPGA vendors started talking about “System Gates” Some folks say that this was a noble attempt to use terminology that ASIC designers could relate to, while others believe it was purely a callow marketing ploy that didn’t do anyone any favors. Each LC/LE was formed from one or more look-up tables (LUTs) coupled with some additional logic like one or more register bits and one or more multiplexers. Note: As an aside, you may also be interested in my article What's the number of ASIC versus FPGA design starts? ( Click Here to see that article).Įarly FPGAs predominantly consisted of programmable fabric in the form of “islands” of logic floating in a “sea” of programmable interconnect. OK, here we go… In the ASIC world it’s common to talk about “equivalent gates.” The idea is to convert each logic function in an ASIC design (multiplexer, register, whatever) into some number of equivalent gates – say 2-input NAND gates – and then add them all together to say “This design has XXX equivalent gates.” This provides a way to compare different ASICs so that one can say “Ha! Mine is bigger than yours (and so is my ASIC)!” In most of Altera’s product datasheets only LEs are mentioned, but not system gates – is the present FPGA emphasis more on LEs instead of system gates? What would be the count of LEs equivalent to 230K system gates in FPGAs and CPLDs. Hello Max, Would you please provide me any details about relation between Logic Elements (LEs) and System Gates count. Arrgghhh! Will this never end? I just received an email from someone who asked: ![]()
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